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SUMMIT
MICROELECTRONICS, Inc.
SMS8198
Philips TriMediaTM Processor Companion Supervisor With a 16K-bit 2-wire Serial Memory
FEATURES * Designed to operate with the Philips TriMedia Processor * Coordinating the System Reset Function and Providing the Processor's Configuration Memory * Multiple VTRIP Thresholds - No External Components Required * Guaranteed Reset Assertion to VCC -1V * Reset is an I/O - Allows System Reset Clean up - Provides a De-bounced Manual Reset Function * Industry Standard 2-wire Serial Interface * Hardware Write Lockout Function * High Reliability - Endurance: 100,000 write cycles - Data Retention: 100 Years OVERVIEW The SMS8198 is a precision supervisory circuit designed specifically as a companion chip for the Philips TriMedia Processor family. The SMS8198 monitors the power supply and holds the system in reset whenever VCC is below the VTRIP threshold. In addition to the supervisory function, the SMS8198 has 16K-bits of nonvolatile memory that is used by the TriMedia processor as the boot memory. The SMS8198 provides 16K-bits of memory that is accessible through the industry standard 2-wire serial interface. By integrating a precision supervisory circuit and the hardware WP input, the SMS8198 becomes the perfect companion chip for the Philips TriMedia processor family. Its functions are integral to the boot hardware operation of the TriMedia processors.
BLOCK DIAGRAM
VCC 8
SCL SDA
6 5
NONVOLATILE MEMORY ARRAY
WRITE CONTROL
7
WP
2 PROGRAMMABLE RESET PULSE GENERATOR
TRI_RESET#
+ -
VTRIP
RESET CONTROL
1.26V 4 GND
SUMMIT MICROELECTRONICS, Inc. * 300 Orchard City Drive, Suite 131 * Campbell, CA 95008 * 2036 T BD 2.0
Telephone 408-378-6461
*
Fax 408-378-6586
*
www.summitmicro.com
(c) SUMMIT MICROELECTRONICS, Inc. 2000 2036 5.0 4/18/00
Characteristics subject to change without notice
1
SMS8198
Camera Audio
4.7K 10K 4.7K
4.7K
Tri Media Processor
WP TRI_RESET# TRI_RESET#
VCR/Monitor
Audio SCL SDA System Boot Block
SMS8198
Local Reset Peripheral Peripheral
PCI_RESET#
PCI Bus
2036 ILL16.0
Figure 1. Typical Implementation of the SMS8198 and TriMedia Processor
The boot hardware operation begins with the assertion of the reset signal TRI_RESET#. The TRI_RESET# output from the SMS8198 is guaranteed to be valid at VCC -1.0V. The reset output is asserted whenever VCC is less than the VTRIP threshold and will remain asserted after VCC is >V TRIP for the duration of t PURST. Whenever the TRI_RESET# is active the memory will be write protected. In addition to the reset write protection feature, pin 7 can be tied to a pull-up to disable the write function of the memory. This effectively turns the memory array into an inexpensive boot ROM.
After reset is de-asserted, only the system boot block is allowed to operate. At this point the TriMedia processor takes over and begins to download data from the memory array into its system boot block. The data downloaded contains configuration data to set up the TriMedia processor and to load special ID information into the PCI configuration space register. The ID information is published in the PCI configuration register to provide the 16 bit Subsystem ID and Subsystem Vendor ID. It should be noted that both the threshold and the tPURST pulse width are programmable. Not only does this provide maximum flexibility to the designer, but, as the processor operating voltage levels migrate downwards, the SMS8198 can be programmed to following this downward trend. The values can be selected from the ordering information table and the devices specified as standard off-the-shelf items.
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SMS8198
tGLITCH
VTRIP VRVALID
tRPD tPURST tPURST
VCC
TRI_RESET#
tRPD
2036 T fig02 2.0
Figure 2. Reset Output Timing
RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS TA = -40C to +85C Symbol VTRIP Parameter Reset Trip Point Part no. Suffix A (or) Blank B 2.7 tPURST tRPD VRVALID tGLITCH VOLRS VOHRS Reset Timeout VTRIP to RESET Output Delay RESET Output Valid to VCC min. Guarantee Glitch Reject Pulse Width note 1 RESET Output Low Voltage IOL = 1mA RESET High Voltage Output IOH = 800A Min. 4.250 4.50 2.55 Typ. 4.375 4.625 2.65 200 5 1 30 0.4 Max. 4.5 4.75 2.75 Unit V V V ms s V ns V
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3
SMS8198
PIN CONFIGURATIONS TRI_RESET# - is an active low open drain output. It is driven low whenever VCC is below VTRIP. TRI_RESET# is also an input and can be used to debounce a switch input or perform signal conditioning. The TRI_RESET# pin does have an internal pull-up and should be left unconnected if the signal is not used in the system. However, when the pin is tied to a system TRI_RESET# line an external pull-up resistor should be employed. Write Protect (WP) - All write operations can be disabled by maintaining WP > VIH. No Connects (NC) - The no connect inputs are unused by the SMS8198; however, to insure proper operation they can be unconnected or tied to ground. They must not be tied to VCC. ENDURANCE AND DATA RETENTION PIN NAMES SDA SCL TRI_RESET# GND VCC WP NC Serial Data I/O Serial Clock Input Reset Output Ground Supply Voltage Write Protect No Connect The SMS8198 is designed for applications requiring up to 100,000 erase/write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles. RESET CONTROLLER DESCRIPTION The device provides a precise reset output to a microcontroller and it's associated circuitry ensuring correct system operation during power-up/down conditions and brownout situations. The output is open drain, allowing control of the reset function by multiple devices. During power-up the reset output remains in a fixed active state until VCC passes through the reset threshold and remains above the threshold for tPURST. The reset output is valid whenever VCC is equal to or greater than 1V. If VCC falls below the threshold for more than tGLITCH the device will immediately generate a reset and drive the output. The reset pin is an I/O; therefore, forcing the pin to the active state can also manually reset the device. Because the I/O needs to be an open drain, the internal timer can only be triggered by the leading edge of the input. The resulting reset output will either be tPURST, or the externally applied reset signal, whichever is longer. This can provide an affective debounce or reset signal extender solution.
8-Pin SOIC
NC TRI_RESET# NC GND
1 2 3 4
8 7 6 5
VCC WP SCL SDA
2036 T PCon 2.0
PIN DESCRIPTIONS Serial Clock (SCL) - The SCL input is used to clock data into and out of the device. In the WRITE mode, data must remain stable while SCL is HIGH. In the READ mode, data is clocked out on the falling edge of SCL. Serial Data (SDA) - The SDA pin is a bidirectional pin used to transfer data into and out of the device. Data may change only when SCL is LOW, except START and STOP conditions. It is an open-drain output and may be wireORed with any number of open-drain or open-collector outputs.
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SMS8198
SCL
Data must remain stable while clock is HIGH.
Change of data allowed
Data must remain stable while clock is HIGH.
SDA In tHD:DAT tSU:DAT tHD:DAT
2036 ILL4.0
Figure 3. Input Data Protocol
SCL from Master Data Output from Transmitter Data Output from Receiver Start Condition
1
8
9
tAA
tAA
ACKnowledge
2036 ILL6.0
Figure 4. Acknowledge Response From Receiver
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5
SMS8198
CHARACTERISTICS OF THE I2C BUS General Description The I2C bus was designed for two-way, two-line serial communication between different integrated circuits. The two lines are: a serial data line (SDA), and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus. Data transfer between devices may be initiated with a START condition only when SCL and SDA are HIGH (bus is not busy). Input Data Protocol One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock HIGH time, because changes on the data line while SCL is HIGH will be interpreted as start or stop condition (See Figure 2). START and STOP Conditions When both the data and clock lines are HIGH, the bus is said to be not busy. A HIGH-to-LOW transition on the data line, while the clock is HIGH, is defined as the "START" condition. A LOW-to-HIGH transition on the data line, while the clock is HIGH, is defined as the "STOP" condition (See Figure 3). DEVICE OPERATION The SMS8198 is a 16,384-bit serial E2PROM. The device supports the I2C bidirectional data transmission protocol. The protocol defines any device that sends data onto the bus as a "transmitter" and any device which receives data as a "receiver." The device controlling data transmission is called the "master" and the controlled device is called the "slave." In all cases, the SMS8198 will be a "slave" device, since it never initiates any data transfers. Acknowledge (ACK) Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either the master or the slave, will release the bus after transmit1
ting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to ACKnowledge that it received the eight bits of data (See Figure 4). The SMS8198 will respond with an ACKnowledge after recognition of a START condition and its slave address byte. If both the device and a write operation are selected, the SMS8198 will respond with an ACKnowledge after the receipt of each subsequent 8-bit word. In the READ mode, the SMS8198 transmits eight bits of data, then releases the SDA line, and monitors the line for an ACKnowledge signal. If an ACKnowledge is detected, and no STOP condition is generated by the master, the SMS8198 will continue to transmit data. If an ACKnowledge is not detected, the SMS8198 will terminate further data transmissions and awaits a STOP condition before returning to the standby power mode. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see figure 5). For the SMS8198 this is fixed as 1010bin. Word Address The next three bits of the slave address are an extension of the array's address and are concatenated with the eight bits of address in the word address field, providing direct access to the 2,048 X 8 array. Read/Write Bit The last bit of the data stream defines the operation to be performed. When set to "1," a read operation is selected; when set to "0," a write operation is selected.
DEVICE IDENTIFIER
HIGH ORDER WORD ADDRESS
0
1
0
A10
A9
A8
R/W
2036 ILL7.0
Figure 5. Slave Address Byte
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SMS8198
WRITE OPERATIONS The SMS8198 allows two types of write operations: byte write and page write. The byte write operation writes a single byte during the nonvolatile write period (tWR). The page write operation allows up to 16 bytes in the same page to be written during tWR. Byte WRITE After the slave address is sent (to identify the slave device, specify high order word address and a read or write operation), a second byte is transmitted which contains the low 8 bit addresses of any one of the 2,048 words in the array. Upon receipt of the word address, the SMS8198 responds with an ACKnowledge. After receiving the next byte of data, it again responds with an ACKnowledge. The master then terminates the transfer by generating a STOP condition, at which time the SMS8198 begins the internal write cycle. While the internal write cycle is in progress, the SMS8198 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 6 for the address, ACKnowledge and data transfer sequence. Page WRITE The SMS8198 is capable of a 16-byte page write operation. It is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first data word, the master can transmit up to 15 more words of data. After the receipt of each word, the SMS8198 will respond with an ACKnowledge. The SMS8198 automatically increments the address for subsequent data words. After the receipt of each word, the four low order address bits are internally incremented by one. The high order five bits of the address byte remain constant. Should the master transmit more than sixteen words, prior to generating the STOP condition, the address counter will "roll over," and the previously written data will be overwritten. As with the byte-write operation, all inputs are disabled during the internal write cycle. Refer to Figure 6 for the address, ACKnowledge and data transfer sequence.
Acknowledges Transmitted from SMS8198 to Master Receiver
If single byte-write only, Stop bit issued here.
Acknowledges Transmitted from SMS8198 to Master Receiver
SDA Bus Activity
1010
A AAR 10 9 8 W
A C Word Address K
AAAAAAAA 76543210
A C K
Data Byte n
A C K
A
Data Byte n+1 C
K
DDDDDDDD 76543210
Data Byte n+15 C
K
DDDDDDDD 76543210
A
0
DDDDDDDD 76543210
S T Device A10,A9,A8 Type A R Address Read/Write T 0= Write
S T O P
Slave Address
Master Sends Read Request to Slave Master Writes Word Address to Slave Master Writes Data to Slave Master Writes Data to Slave Master Writes Data to Slave
Master Transmitter to Slave Receiver
Master Transmitter to Slave Receiver
Master Transmitter to Slave Receiver
Master Transmitter to Slave Receiver
Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver
2036 ILL8.0
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Shading Denotes SMS8198 SDA Output Active
Figure 6. Page/Byte WRITE Mode
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7
SMS8198
Acknowledge Polling When the SMS8198 is performing an internal WRITE operation, it will ignore any new START conditions. Since the device will only return an acknowledge after it accepts the START, the part can be continuously queried until an acknowledge is issued, indicating that the internal WRITE cycle is complete. To poll the device, give it a START condition, followed by a slave address for a WRITE operation (See Figure 7).
Internal WRITE Cycle In Progress; Begin ACK Polling
READ OPERATIONS Read operations are initiated with the R/W bit of the identification field set to "1." There are four different read options: 1. 2. 3. 4. Current Address Byte Read Random Address Byte Read Current Address Sequential Read Random Address Sequential Read
Issue Start
Issue Slave Address and R/W = 0
Issue Stop
Current Address Byte Read The SMS8198 contains an internal address counter which maintains the address of the last word accessed, incremented by one. If the last address accessed (either a read or write) was to address location n, the next read operation would access data from address location n+1 and increment the current address pointer. When the SMS8198 receives the slave address field with the R/W bit set to "1," it issues an acknowledge and transmits the 8-bit word stored at address location n+1. The current address byte read operation only accesses a single byte of data. The master does not acknowledge the transfer, but does generate a stop condition. At this point, the SMS8198 discontinues data transmission. See Figure 8 for the address acknowledge and data transfer sequence.
ACK Returned?
No
Yes (Internal WRITE Cycle is completed) Next operation a WRITE? Yes Issue Byte Address Issue Stop No
Proceed with WRITE
Await Next Command
2036 ILL9.0
Figure 7. Acknowledge Polling
SDA Bus Activity
1
A AAR 10 9 8 W
A C K
Data Byte
1010
1
DDDDDDDD 76543210
1
S T O P
S T Device Type A10,A9,A8 A Address Read/Write R 1= Read T
Slave Address
Master sends Read request to Slave
Lack of ACK (low) from Master determines last data byte to be read Slave sends Data to Master Slave Transmitter to Master Receiver
Master Transmitter to Slave Receiver
Shading Denotes SMS8198 SDA Output Active
2036 ILL10.0
Figure 8. Current Address Byte Read Mode
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8
SMS8198
Random Address Byte Read Random address read operations allow the master to access any memory location in a random fashion. This operation involves a two-step process. First, the master issues a write command which includes the start condition and the slave address field (with the R/W bit set to WRITE) followed by the address of the word it is to read. This procedure sets the internal address counter of the SMS8198 to the desired address. After the word address acknowledge is received by the master, the master immediately reissues a start condition followed by another slave address field with the R/W bit set to READ. The SMS8198 will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. At this point, the master does not acknowledge the transmission but does generate the stop condition. The SMS8198 discontinues data transmission and reverts to its standby power mode. See Figure 9 for the address, acknowledge and data transfer sequence.
SDA Bus Activity
1010
AAAR 10 9 8 W
A C K
Word Address
A C K
AAAR 10 9 8 W
A C K
Data Byte
0
AAA A AA AA 765 4 32 10
1010
1
D DD DD DD D 7 65 43 21 0
1
S T O P
S T Device A10,A9,A8 Type A Address Read/Write R 0= Write T
S T Device A10,A9,A8 A Type Address Read/Write R 1= Read T
Slave Address
Master sends Read request to Slave Master Writes Word Address to Slave
Slave Address
Master Requests Data from Slave
Lack of ACK (low) from Master determines last data byte to be read
Slave sends Data to Master
Master Transmitter to Slave Receiver Shading Denotes SMS8198 SDA Output Active
Master Transmitter to Slave Receiver
Master Transmitter to Slave Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
2036 ILL11.0
Figure 9. Random Address Byte Read Mode
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9
SMS8198
Sequential READ Sequential READs can be initiated as either a current address READ or random access READ. The first word is transmitted as with the other byte read modes (current address byte READ or random address byte READ); however, the master now responds with an ACKnowledge, indicating that it requires additional data from the SMS8198. The SMS8198 continues to output data for each ACKnowledge received. The master terminates the sequential READ operation by not responding with an ACKnowledge, and issues a STOP conditions. During a sequential read operation, the internal address counter is automatically incremented with each acknowledge signal. For read operations, all address bits are incremented, allowing the entire array to be read using a single read command. After a count of the last memory address, the address counter will `roll-over' and the memory will continue to output data. See Figure 10 for the address, acknowledge and data transfer sequence.
Acknowledges from SMS8198
Acknowledge from Master Receiver
Lack of Acknowledge from Master Receiver
SDA Bus Activity
1010
S T Device A Type R Address T
AAAR 10 9 8 W
A C Word Address K
AAAAAAAA 76543210
A C K
AAAR 10 9 8 W
A C K
A
First Data Byte C
K
DD DD DD DD 76 54 32 10
Last Data Byte
0
1010
1
DD DD DD DD 76 54 32 10
1
S T O P
A10,A9,A8
Read/Write 0= Write
S T Device A Type A10,A9,A80 R Address Read/Write T
1= Read
Slave Address
Master sends Read request to Slave Master Writes Word Address to Slave
Slave Address
Master Requests Data from Slave Slave sends Data to Master
Lack of ACK (low) determines last data byte to be read
Slave sends Data to Master
Master Transmitter to Slave Receiver
Master Transmitter to Slave Receiver
Master Transmitter to Slave Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Slave Transmitter to Master Receiver
Master Transmitter to Slave Receiver
2036 ILL12.0
Shading Denotes SMS8198 SDA Output Active Figure 10. Sequential READ Operation (starting with a Random Address READ)
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SMS8198
ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ............................................................................................................... -40C to +85C Storage Temperature ..................................................................................................................... -65C to +125C Soldering Temperature (less than 10 seconds) .............................................................................................. 300C Supply Voltage ........................................................................................................................................... 0 to 6.5V Voltage on Any Pin ...................................................................................................................... -0.3V to VCC+0.3V ESD Voltage (JEDEC method) ...................................................................................................................... 2,000V
NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.
DC ELECTRICAL CHARACTERISTICS SMS8198, TA = -40C to +85C, VCC = 2.7V to 5.5V
Symbol ICC ISB ILI ILO VIL VIH VOL VROL Parameter Supply Current (CMOS) Standby Current (CMOS) Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage RESET Low Output Conditions SCL = CMOS Levels @ 100KHz SDA = Open All other inputs = GND or VCC SCL = SDA = VCC All other inputs = GND VIN = 0 To VCC VOUT = 0 To VCC S0, S1, S2, SCL, SDA, RESET S0, S1, S2, SCL, SDA IOL = 3mA VCC = 1.0V, IOL = 100A VCC = 2.7V, IOL = 400A VCC = 4.5V, IOL = 1mA 0.7xVCC 0.4 0.3 0.3 0.4 VCC =5.5V VCC =3.3V VCC =5.5V VCC =3.3V Min Max 3 2 50 25 10 10 0.3xVCC Units mA mA A A A A V V V V V V
2036 PGM T1.1
AC ELECTRICAL CHARACTERISTICS SMS8198, TA = -40C to +85C, VCC = 2.7V to 5.5V
Symbol fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT tI tWR
Parameter SCL clock frequency Clock low period Clock high period Bus free time Start condition setup time Start condition hold time Stop condition setup time Clock to output Data Out hold time SCL and SDA rise time SCL and SDA fall time Data In setup time Data In hold time Noise spike width @ SCL & SDA inputs Write cycle time
Conditions
2.7V to 4.5V Min. 0 4.7 4.0 Max. 100
4.5V to 5.5V Min. 1.3 0.6 1.3 0.6 0.6 0.6 Max. 400
Units kHz s s s s s s
Before new transmission
4.7 4.7 4.0 4.7
SCL low to SDA Data Out valid SCL low to SDA Data Out change
0.3 0.3
3.5 1 0.3
0.2 0.2
0.9 0.3 0.3
s s s s ns ns
250 0 Noise suppresion time constant 100 10
11
100 0 100 10
ns ms
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SMS8198
CAPACITANCE TA = 25C, f = 100KHz Symbol CIN COUT Parameter Input Capacitance Output Capacitance Max 5 8 Units pF pF
2036 PGM T3.0
tR
tF
tHIGH
tLOW
SCL
tSU:SDA tHD:DAT tSU:DAT tSU:STO
tHD:SDA
tBUF
SDA In
tAA
tDH
SDA Out
2047 Fig07 1.0
Figure 11. Bus Timing
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12
SMS8198
ORDERING INFORMATION
SMS8198 Base Part Number Package S = 8 Lead SOIC
S
A VTRIP Threshold A or Blank = 4.5V B = 4.75V 2.7 = 2.7V
2036 Tree 2.0
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SMS8198
8 Pin SOIC (Type S) Package JEDEC (150 mil body width)
.050 (1.27) TYP. .050 (1.270) TYP. 8 Places
.157 (4.00) .150 (3.80)
.275 (6.99) TYP.
1 .196 (5.00) .189 (4.80)
.030 (.762) TYP. 8 Places
FOOTPRINT
.061 (1.75) .053 (1.35) .020 (.50) x45 .010 (.25)
.0192 (.49) .0138 (.35)
.0098 (.25) .004 (.127) .05 (1.27) TYP.
.035 (.90) .016 (.40)
.244 (6.20) .228 (5.80)
8pn JEDEC SOIC ILL.2
NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. I2C is a trademark of Philips Corporation. (c) Copyright 2000 SUMMIT Microelectronics, Inc.
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